Question Bank
By translation,
a program that was written for a high-level machine is transformed by a translator into a program that can then be executed on a lower level of that machine, without further need for ,
each instruction of a program written for a high-level machine is transformed into a sequence of instructions for a lower level of that machine, then immediately executed, before the same process is applied to the next instruction from ,
a program that is written for a high-level virtual machine is transformed into a program which can be executed on a physical machine .
The data path is defined as:
the connection between input-output devices and the processor,
the representation of data types in the memory of a computing system,
the connection, through buses, between registers, arithmetic-logical unit and back to registers, used for instruction execution,
networks interconnecting computing systems (like the Internet).
The program counter:
is a global variable in a program that is used to count the number of instructions executed, and measure program complexity,
is a register that holds an address to the next instruction that has to be executed,
is a register that holds the instruction that is being executed in a processor,
is an operating system variable that counts the number of processes in execution at a given time.
Microprogramming is
the activity of writing programs that run on microprocessors,
the use of a set of instructions (microinstructions), stored in a memory, that are used to control the data path, for the purpose of executing instructions in one or several data path cycles,
the interaction with input/output devices by issuing commands to controllers (e.g commands for the hard drive controller to read a word from an address),
automated generation of small programs for embedded devices.
A kilobyte is
bits,
bytes,
bits.
A typical use for a demultiplexer circuit is the implementation of
a 1 bit full adder circuit,
a serial-to-parallel convertor,
a parallel-to-serial convertor,
an integer multiplication circuit.
For cache memories, the locality principle refers to:
the fact that memory locations close to the previously used one are likely to be used in the near future,
the fact that memory locations that were accessed recently will likely be accessed again,
the position of cache levels with respect to the processor (on processor, or very near the processor).
Which type of branch instruction causes most delay in a typical five stage pipeline:
unconditional branches,
conditional branches,
none of the branch prediction causes any delay in the pipeline,
both types of branch prediction cause the same amount of delay, on average.
Which of the following are necessary to describe the Instruction Set Architecture level:
the memory model,
the configuration of the cache,
the configuration of registers,
data types,
instructions.
The result of the following addition in 2’s complement representation on 8 bits is:
11101110 and the result is correct,
11101110 but there is an overflow,
11101111 and the result is correct,
11101111 but there is an overflow.
The sequence represents the following number in IEEE 754 single precision floating point representation:
0.0625,
16.25,
41,
221.
[In general] the Instruction Sets are growing larger and larger over time. Why is that?:
because Moore’s law dictates that we double the amount of computation every 2 years
because the RAM (and memory in general) is growing larger and larger each year
because with each new generation of CPU’s more instructions are added; thus growing the list;
because there is an increase in the number of users and the applications that they use
because old OPT codes must be kept for backwards compatibility.
In the Cache, the role of the Dirty bit is to :
signal that the data in the cache is old
There is no such thing as a "dirty bit".
signal that the cache line might contain a different value than the corresponding memory location in RAM;
keep track if there was a Cache Hit or Cache Miss in the previous instruction
None of the above.
Select the correct statements in regard to the Central Processing Unit
Its role is to execute instructions
it contains multiple registers
Each computer has one CPU in it
Uses multiple phases to process each instruction
It controls how the data is written into the RAM memory.
Upon completing the Execute Phase the Control Unit...
transfers control to the memory to store the result of the execution
increments the instruction address
checks if the next memory address contains and instruction or data
clears all registers to prepare the CPU for the next instruction
none of the above.
What is the role of the Clock inside a computer?
It is just unit of measure that helps rank the CPUs by speed.
Its signal is used by the Control Unit to advance the internal operation of the CPU.
Its main role is to allow overclocking and/or underclocking of CPUs.
Keeps track not only of time but also the date and other useful timing variables.
Triggers an electrical signal at a precise and regular interval.
A process socket local address is equal to:
port number + IP address
IP address
port number
IP address + hostname + port number
Network layer protocol that reports on the success or failure of data delivery:
IP
TCP
ARP
ICMP
Which of the following services use UDP?
SMTP
SNMP
FTP
TFTP
DHCP
HTTP
Which of the following devices are layer 2 devices?
bridge
repeater
router
switch
hub
Which of the following IP addresses fall into the CIDR block of ?
What is the network topology where each node is connected to the two nearest nodes so that the entire network forms a circle?
bus
ring
star
bus-star
Which fields are contained within an Ethernet frame header?
source and destination hardware addresses
source and destination network addresses
error correction code
authentication code
Which of the following statements is true regarding a switch?
it creates a single collision domain and a single broadcast domain
it creates separate collision domains but one broadcast domain
it creates separate collision domains and separate broadcast domains
What is a valid IPv4 address example?
144.92.254.253
144-92-43-178
144.92.256.176
144,92,43,178